EasyCKTPower Design Studio
POWER DESIGN STUDIO / CONTROL LOOP

Current Mode Compensator Calculator (OTA Type II)

Design the outer voltage loop of a current-mode buck with an OTA Type II compensator. Enter the controller’s Gci and amplifier gm separately. The inner current loop is assumed fast and stable; slope compensation is outside this model.

Type IIIVoltage Mode · Two Lead PairsType IIVoltage Mode · Lower BandwidthCurrent ModeOuter voltage loop · OTA Type II
60-second Compensation Guide

① Check power stage & controller → ② Set f_c & PM → ③ Auto-design → ④ Apply E24, then recheck f_c, PM & GM

f_c (0 dB Crossover)

Where loop gain crosses 0 dB. Higher f_c can speed response but reduces delay tolerance.

PM

Phase headroom to −180° at f_c. Start at 60° and inspect every gain crossing.

GM

At a −180° phase crossing, GM = −loop gain (dB). No crossing means undetermined in this band.

Zeros / Poles

Zeros add phase lead; poles reduce high-frequency gain. Type II uses one pair, III two, plus an origin pole.

Current Mode uses an OTA Type II outer loop with a fast, stable inner loop assumed. Gci and gm differ. Check the actual IC, tolerances, transients and slope compensation separately.

TI · Op-Amp / OTA compensation
Plots & resultsR/C parts

f_c (0 dB Crossover)——
Phase Margin (PM, min)——
Gain Margin (GM, min)—Within the plotted band
Divider-Implied DC Output——
Loop

Gain dB

Phase °

Shading marks frequencies above fSW/10. Averaged results there are indicative and do not validate switching or sampling effects.

03Compensation Network / R-C Values

After rounding, check component tolerances, amplifier bandwidth and output swing.

Transfer Functions / Model Scope
  • Type II/III: single-phase CCM buck with a resistive load and ideal op-amp. R1 connects VOUT to the inverting input, so the divider ratio is not multiplied into loop gain again.
  • Current Mode: ideal closed inner current loop with an OTA Type II outer voltage loop. Gci maps COMP voltage to average IL. Inner peak/average current-loop dynamics, slope compensation and subharmonic instability are not calculated.
  • Additional delay uses exp(−sTd). Phase margin alone does not guarantee stability at every operating point. Check multiple crossings, the real IC model, tolerances and load transients.
TI SLVA662 · Op-Amp / OTA compensation
ADI · Compensation network design
Total visits—

Loading visit counts.